Referring to FIG. 1, a conventional fiber-optic communication module 100, which may be used in a digital fiber-optic communication system, typically includes a fiber-optic receiver section 101, a fiber-optic transmitter section 102, and a controller section 103, which are all coupled via an internal bus 105. In some communication modules (not shown), the internal bus is an analog bus. However, because of the many signals to be communicated between the receiver, transmitter and controller, the number of wire traces needed in such an analog bus may become too numerous for practical application. Therefore, the internal bus 105 is a digital bus. In operation, the controller 103 controls and monitors the receiver 101 and transmitter 102 via the bus 105.
The communication module 100 also communicates with one or more external devices 120, via an external bus 107. Typical external devices 120 include diagnostic devices and configuration devices. External devices are often used during manufacturing of the communication module 100 for diagnostics during processing and verification after manufacturing. Furthermore, external devices are typically used to download programmable capabilities to the communication module in order to establish a desired performance setting. The external bus 107 is coupled to the transmitter 102, (although it may be coupled to the controller 103 or the receiver 101). This allows the external device 120 to communicate with the receiver 101 and controller 103 via the transmitter 102 and bus 105, which act as an interface to the external device 120.
The external bus 107, which is typically a two-wire standard serial interface, may be used to communicate to and from the external device 120 imperative data about the module, such as, for example, specialized factory data and diagnostics data. During manufacture, testing, qualification, and failure analysis, it is advantageous to be able to store and retrieve this imperative data which may be stored in registers internal to the module 100. It is also advantageous to operate the module 100 in unique ways to test special features or to provide specialized user functionality for specific applications. Therefore, imperative data about these specialized functions may be retrieved from registers that reside within the module 100 as well. However, limited address space and the need to keep proprietary imperative data from an end user present a problem because all registers coupled to the busses 105 and 107 are typically accessible.
In the communication module 100, all electronic components that are coupled to a respective bus (either internal bus 105 or external bus 107) are typically assigned a predetermined bus address for each register or sets of registers. This is referred to as an address scheme. Typically, a standard two-wire serial bus may assign 16 addresses that are uniquely identified by 4 bits of an 8-bit address. The remaining 4 bits in the 8-bit address are unused or designate other functions, such as a read or write command. Other address schemes may have different bit lengths for addresses and may employ the non-address bits for other purposes.
One wire of the standard two-wire serial bus 105 is a clock line that receives a clock signal from the bus master and the other line is a data line that receives data from a sender. When a sender (a component initiating a write or read) is to write data to or read data from another component (a receiver), the sender places the address of the intended register within the receiver component on the bus; i.e., sends an 8-bit address on the data line, which is clocked by the bus master. Each register or set of registers that is assigned an address in the address scheme and coupled to the bus receives the 8-bit address at an interface-comparing device (not shown), which determines whether the 4-bits of the 8-bit address on the data line matches the 4-bit address that corresponds to its respective register. If a match is found, the interface-comparing device returns an acknowledgment bit on the data line to indicate that the address exists and is ready to receive further 8-bit packets of data (offset, written data, etc.). Typically, only one register or set of registers may be assigned a particular address in an address scheme such that its respective interface-comparing device is the only device that can return an acknowledgement bit in response to the particular address.
Registers that are associated with a respective address within an address scheme are visible, i.e., readable and writable, to all electronic components and devices that are connected to the external 107 and internal 105 busses, respectively. This is problematic because it is sometimes desired to not allow all components and devices to write to and read from registers that store proprietary or other imperative data or to change the operating mode of the module itself. As such, it is desired to maintain the anonymity of the address of any registers containing imperative data and only allow access during troubleshooting, fault analysis, or other similar situations.
One solution is to implement an entire separate (from the external bus 107) bus connection (not shown) for data exchange and communication between an external device 120 and the registers for storing the imperative data. This solution may increase the complexity and pinout of the module 100, and may introduce noise on the internal bus 105. Furthermore, it is often difficult to physically probe with the internal bus 105 which is coupled to internal registers that store the imperative data from the outside of the communication module 100 because the internal registers or the internal bus 105 may be within an intermediate, and thus, inaccessible, layer of a printed circuit board. Thus, it is difficult to physically probe analog or digital internal test points and is problematic in the high volumes necessary.